How to Create a Hierarchy in Verilog Creating a hierarchy is a fundamental concept in Verilog. It allows you to break down a complex digital system into smaller, manageable, and reusable pieces called modules. This modular approach mirrors real-world hardware design, where complex chips are built from smaller sub-circuits. 1. Understand the Module
The module is the basic building block in Verilog. Think of it as a black box with inputs and outputs. To build a hierarchy, you define these individual blocks first, and then connect them inside a top-level module. A standard module template looks like this:
module module_name ( input wire clk, input wire data_in, output wire data_out ); // Logic goes here endmodule Use code with caution. 2. Define the Sub-Modules (The Components)
Before you can build a hierarchy, you need components to instantiate. Let’s create two simple sub-modules: an AND gate and an OR gate. The AND Gate Module
module and_gate ( input wire a, input wire b, output wire out ); assign out = a & b; endmodule Use code with caution. The OR Gate Module
module or_gate ( input wire a, input wire b, output wire out ); assign out = a | b; endmodule Use code with caution. 3. Instantiate Sub-Modules in a Top-Level Module
To create the hierarchy, you create a higher-level module (often called top) and place instances of your sub-modules inside it. This process is called instantiation. When instantiating a module, you must provide: The Type: The name of the sub-module you are using.
The Instance Name: A unique name for this specific copy of the module.
The Port Connections: A list matching your top-level signals to the sub-module’s pins. Connection Methods
There are two ways to connect ports in Verilog. Always prefer Connection by Name as it prevents bugs when module definitions change.
Connection by Name (Recommended): Uses a dot (.) followed by the sub-module port name, with the local signal in parentheses.
Connection by Position (Not Recommended): Matches signals purely by the order they appear in the sub-module definition. The Top-Level Module Example
Here is how we use our and_gate and or_gate to build a larger circuit:
module top_level_circuit ( input wire in1, input wire in2, input wire in3, output wire final_out ); // Internal wire to connect the two gates wire intermediate_connection; // Instantiating the AND gate (Named connection) and_gate and_inst1 ( .a(in1), .b(in2), .out(intermediate_connection) ); // Instantiating the OR gate (Named connection) or_gate or_inst1 ( .a(intermediate_connection), .b(in3), .out(final_out) ); endmodule Use code with caution. 4. Best Practices for Verilog Hierarchy
To keep your hierarchical designs clean, efficient, and easy to debug, follow these industry standards:
One Module Per File: Keep each module in its own separate .v file. Name the file exactly like the module (e.g., and_gate.v).
Keep Top-Level Clean: The top-level module should ideally contain only wiring and instantiations. Avoid putting heavy combinational or sequential logic directly into the top module.
Use Descriptive Instance Names: If you instantiate three multiplexers, name them mux_left, mux_right, and mux_output instead of m1, m2, and m3.
Check Bit Widths: Ensure the wires in your top-level module exactly match the bit widths of the sub-module ports they connect to. Mismatched widths cause silent errors or unexpected trimming.
Building a hierarchy in Verilog requires defining your low-level modules, creating internal wires in a top-level module to act as a breadboard, and instantiating the components using explicit named port connections. This keeps your code clean, readable, and ready for hardware synthesis.
If you want to take this design further, let me know. I can show you how to:
Add parameters to make your hierarchical modules reusable for different bit widths.
Write a testbench to simulate and verify this hierarchical design.
Convert this design to use SystemVerilog implicit port connections (.*) for faster coding.
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